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TV-Stereo Processor
Preliminary Data
TDA 6812-5
Bipolar IC
Features High quality stereo signal processing High S/N ratio I2C Bus Clipping detector and clock generator NICAM or AM sound inputs Volume control Universal audio interface for DOLBY, EQUALIZER, SURROUND SOUND features q Multiplex 3-SCART connections q Independent headphones
q q q q q q q
P-DIP-40-2
Type TDA 6812-5
Ordering Code Q67000-A5127
Package P-DIP-40-2
TDA 6812-5 is a complete system for stereo TV-sound, controlled on an I2C Bus. The device is made up of three functional blocks. 1. Stereo Processing with High Quality (better than DIN 45500; suitable for NICAM and CD for G-standard with I2C-controlled crosstalk compensation; selectable gain 0/6 dB a) Three stereo AF-inputs b) Random switching of all inputs to all outputs c) Stereo SCART-interface d) Stereo loudspeaker signal section with volume precontrol, treble/bass control, enlargement of quasi-stereo/stereo sound base, separate L/R-volume control, equalizer interface after tone control e) Stereo headphones signal section with Ch1/Ch2 and volume control 2. TV-Identification-Signal Decoder a) Active pilot-tone filter b) Phase-independent rectifier with very narrow bandwidth for identification-signal decoding c) Digital integrator for noise rejection d) Multiplexer for cyclic scanning for stereo or dual-sound identification e) Externally synchronized PLL for reference-signal generation: synchronization with line sync pulse or 62.5-kHz clock, integrated crystal oscillator and 4-MHz crystal, or with external 4-MHz timing signal
113
06.94
TDA 6812-5
3. Control a) I2C Bus interface with listen/talk function b) Control of entire audio processing c) Reading of clipping detector d) Control of identification-signal decoder e) Reading of identification-signal decoder f) Test modes
Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Function AF-input mono, left, sound 1 (adjustable) Bias AF-operating point AF-input, right, sound 2 N.C. 54-kHz input 54-kHz filter SCART-input 1, left SCART-input 1, right SCART-input 2, left SCART-input 2, right SCART-input 3, left SCART-input 3, right AF-output SCART (mono, sound 1, left) AF-output SCART (mono, sound 2, right) Output port 1 (open collector) Output port 2 (open collector) Phase shifter quasi-stereo Phase shifter quasi-stereo Cut-off frequency bass (sound base), left Cut-off frequency bass (sound base), right AF-output, loudspeaker, right AF-output, loudspeaker, left N.C. AF-input, volume control, right
Semiconductor Group
114
TDA 6812-5
Pin Functions (cont'd) Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Function AF-input, volume control, left AF-output, equalizer, right AF-output, equalizer, left Cut-off frequency treble, left Cut-off frequency treble, right AF-output, headphones, right AF-output, headphones, left + VS (supply voltage) I2C Bus SCL I2C Bus SDA Input line sync pulse (4 x H-pulse), crystal oscillator Identification-signal decoder filter N.C. Identification-signal decoder, filter Identification-signal decoder, PLL-filter Ground
Semiconductor Group
115
TDA 6812-5
Block Diagram Semiconductor Group 116
TDA 6812-5
Circuit Description Signal Section The dematrixing and switching of multichannel TV-sound signals are performed in the matrix and switch section by the dual-carrier method. Crosstalk compensation is on the sound 1 input. The compensation stage has a range of 3 dB with a smallest increment of 0.2 dB, and gain can also be switched between 0 and 6 dB. In addition to the two inputs for the demodulated sound carriers, there are three dual-channel SCART-inputs. The two matrix AF-inputs can be bypassed internally so that decoded stereo signals of other systems (NICAM) can also be processed. The switch section terminates in the SCART-output and signal paths for the loudspeaker and headphones outputs. AF-inputs can be randomly switched to AF-outputs (8-6 matrix). In the loudpeaker signal path there is an inital volume control with a range of 0/- 15 dB and an increment of 1.25 dB. In conjunction with the main volume control that follows the tone control, very high overdriving immunity is ensured. The switchable quasi-stereo section that follows produces a stereo listening effect for mono signals through a 180 oC phase shift at mid-range frequencies (approx. 1 kHz) in one channel. The following bass control has an increment of 3 dB in its setting range of + 15/- 12 dB. The cut-off frequency for each channel is set by an external capacitor. The circuit for enlarging the stereo sound base can be cut in for stereo signals to make the aural impression even more stereo-like by frequency-dependent antiphase crosstalk of 55 %. This works with the same cut-off frequency as the bass control, but the function is largely independent. The treble control, whose cut-off frequency is also set by an external capacitor, likewise has an increment of 3 dB in a setting range of 12 dB. The main value control with maximum gain of 10 dB, which can be adjusted separately for L and R, terminates the loudspeaker signal path. 57 steps with an increment of 1.25 dB mean a setting range of 71.25 dB. Functions like balance or loudness are implemented by software setting of the appropriate tone and volume controls. In the tonecontrol section there is a clipping detector that can be read on the I2C Bus and enables automatic volume correction by the controller. After each reading the clipping bit is reset, which enables a renewed check for clipping with each I2C Bus read operation. The headphones signal path includes a volume control with joint L/R-setting. 32 increments of 2 dB produce a range of 62 dB (31 x 2 dB = 62 dB). Identification-Signal Decoder The input of the identification-signal decoder consists of an operational amplifier for selectivity of the pilot tone and its sidebands with an external LC-circuit. The signal is fed to a phase-independent active bandpass filter of very narrow bandwidth (externally adjustable) that detects the presence of the lower sideband of the pilot carrier modulated with the identification signal. The center frequency of the filter is switched back and forth between dual and stereo by a multiplexer (software-controlled timing). The multiplexer halts when a sideband is detected. This first "detected" criterion is freed from noise by a digital integrator followed by a comparator and can then be read on the I2C Bus (talker) as stereo or dual mode. The C controls the signal paths. All necesssary timing signals are derived from a fast settling PLL synchronized by a reference frequency. This reference must be sufficiently identical to the horizontal frequency, but no phase locking is necessary. This means that it is possible to use the crystal-controlled frequency of 62.5 kHz that is often found in PLL-tuning systems. As further alternatives there is an integrated crystal oscillator that requires a 4-MHz crystal, or it is possible to use a clock frequency of 1 or 4 MHz.
Semiconductor Group
117
TDA 6812-5
Control Section All functions are controlled by an I2C Bus interface which can be both a listener and a talker. The currently valid data are stored in a latch block. The telegram structure is as follows: start condition - chip address - any number of bytes - stop condition The following conditions apply to the data bytes: Before the actual data byte (with setting information) a subaddress byte must always be transmitted, which the I2C Bus still interprets as a data byte. Example: Headphones (HP) volume is to be increased in several steps.
Right Start condition Chip address 84 (Hex) Subaddress volume HP 03 (Hex) Volume Step 8 08 (Hex) Subaddress volume HP 03 (Hex) Volume step 9 09 (Hex) Subaddress volume HP 03 (Hex) Volume Step 10 0A (Hex) Stop condition
Wrong Start condition Chip address 84 (Hex) Subaddress volume HP 03 (Hex) Volume Step 8 08 (Hex) Volume step 9 09 (Hex) Volume Step 10 0A (Hex) Stop condition
Different subaddresses can be used within a telegram, ie without a new start condition. But the change between listener and talker must always be made by stop condition - start condition - chip address. A start condition and a chip address (talk) must always be transmitted before reading. This loads the data that are to be read out on the I2C Bus interface for transfer to the C. Chip Address MSB 1 * 0 * 0 * 0 * 0 * 1 * 0 LSB R/W
R/W = 0 Read (Listen) R/W = 1 Write (Talk)
Semiconductor Group
118
TDA 6812-5
Subaddress Bytes MSB Volume precontrol Volume left speaker Volume right speaker Volume headphones Treble/bass Switching byte I Switching byte II Switching byte III Switching byte IV Crosstalk compensation Setting Bytes a) Volume Precontrol MSB Maximum volume Max. - 1 Min. + 1 Minimum volume Power ON H= H= Q= Q= 0 1 0 1 X X X X 0 * H H H H 0 * Q Q Q Q 0 * 0 0 1 1 0 * 0 0 0 1 0 * 0 0 1 0 0 * 0 1 1 0 0 LSB X X X X 1 X X X X X X X X X X * X X X X X X X X X X * X X X X X X X X X X * X X X X X X X X X X * 0 0 0 0 0 0 0 1 1 0 * 0 0 0 0 1 1 1 0 0 1 * 0 0 1 1 0 1 1 0 0 0 LSB 0 1 0 1 0 0 1 0 1 1
Identification-signal decoder synchronization with fH = 15.625 kHz; power ON Identification-signal decoder synchronization with 4 x fH (must be 1 for operation with crystal or 4-MHz reference frequency) PLL synchronization with line sync pulse; power ON PLL synchronization with crystal oscillator (the bit for H must also be set to 1)
b) L/R-Loudspeaker Volume MSB Maximum volume Max. - 1 Max. - 15 Max. - 55 Power ON X X X X 0 * X X X X 0 * 1 1 1 0 0 * 1 1 1 0 0 * 1 1 0 1 0 * 1 1 0 0 0 * 1 1 0 0 0 LSB 1 0 0 0 1
Semiconductor Group
119
TDA 6812-5
c) Headphones Volume MSB Maximum volume Max. - 1 Max. - 15 Max. - 31 Power ON T2 T2 T2 T2 0 * T1 T1 T1 T1 0 * T0 T0 T0 T0 0 * 1 1 1 0 0 * 1 1 0 0 0 * 1 1 0 0 0 * 1 1 0 0 0 LSB 1 0 0 X 1
T0, T1 and T2 are test bits and must be set to 0 for normal operation. d) Crosstalk Compensation Matrix (sound 1) MSB Maximum gain Max. - 1 Gain 0 dB Minimum gain Minimum gain Power ON e) Treble / Bass MSB Linear Max. treble, lin. bass Max. treble, lin. bass Min. treble, lin. bass Min. treble, lin. bass Lin. treble, max. bass Lin. treble, max. bass Lin. treble, max. bass Lin. treble, min. bass Lin. treble, min. bass Max. treble, max. bass Min. treble, min. bass Power ON 1 1 1 0 0 1 1 1 1 1 1 0 0 MSB treble * 0 1 1 1 0 0 0 0 0 0 1 0 0 * 0 0 X 0 X 0 0 0 0 0 X X 0 * 0 0 X 0 X 0 0 0 0 0 X X 0 LSB treble * 1 1 1 1 1 1 1 1 0 0 1 0 0 MSB bass * 0 0 0 0 0 1 1 1 1 0 1 0 0 * 0 0 0 0 0 0 X 1 0 X X X 0 LSB 0 0 0 0 0 1 1 X 0 X 1 X 1 LSB bass X X X X X X * X X X X X X * X X X X X X * 1 1 1 0 0 0 * 1 1 0 0 0 0 * 1 1 0 0 0 0 * 1 1 0 0 0 0 LSB 1 0 0 1 X 1
Semiconductor Group
120
TDA 6812-5
f) Switching Bytes I, II, III Switching Byte I Switching byte II Switching byte III MSB L3 0 * L2 0 * L1 0 SCART-output Headphones output Loudspeaker output * L0 0 * R3 0 * R2 0 * R1 0 LSB R0 1 Power ON
L0 thru L3 left output, R0 thru 3 right output.
L3 0 0 0 0 0 0 0 0 1 1
L2 0 0 0 0 1 1 1 1 0 0
L1 0 0 1 1 0 0 1 1 0 0
L0 0 1 0 1 0 1 0 1 0 1
Selected Input MUTE AF-input left, mono, sound 1 AF-input right, sound 2 AF-input left, dematrixed SCART 1 left SCART 1 right SCART 2 left SCART 2 right SCART 3 left SCART 3 right
Assignment R3 thru R0 is identical to L3 thru L0.
Semiconductor Group
121
TDA 6812-5
g) Switching Byte IV MSB MPX0 * MPX1 * QSt * BE * Mono * P1 * P2 LSB Matrix
MPX0 0 0 1
MPX1 0 1 0
MPX-Period 2s 4s 8s Power-ON
Recommended C36,38 1 F 2.2 F 4.7 F
Perm. Xtal Tolerances 20 ppm 10 ppm 5 ppm
Settings specially recommended for crystal operation 0 0 0 1 2s 4s 470 nF 330 nF 40 ppm 70 ppm
MXP-period = 2 s means that identification-signal decoder searches 1 s for dual and 1 s for stereo. It is basically permissible, for the given C36,38, to make the MPX period longer, but not shorter. QSt QSt BE BE Mono Mono P1 P1 P2 P2 Matrix Matrix = = = = = = = = = = = = 0 1 0 1 0 1 0 1 0 1 0 1 Quasi-stereo OFF; power ON Quasi-stereo ON Stereo base enlargement OFF; power ON Stereo base enlargement ON Identification-signal decoder set to stereo and held; power ON Normal operation of identification-signal decoder Port 1 (open collector) low (low-impedance); power ON Port 1 high (high impedance) Port 2 (open collector) low (low-impedance); power ON Port 2 high (high impedance) Gain matrix 0 dB Gain matrix 6 dB; power ON
h) Talk Mode MSB St 0 1 0 1 CL = 1 * D 0 0 1 1 * T3 * T4 * T5 * CL * X LSB X
Decoder detects mono Decoder detects stereo Decoder detects dual Suppressed internally
Loudspeaker signal path at clipping limit (CL is automatically reset after each reading operation)
T3 thru T5 are test bits.
Semiconductor Group
122
TDA 6812-5
Absolute Maximum Ratings TA = 0 to 70 oC; all voltages relatives to VSS Parameter Supply voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-voltage Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current Max. DC-current ESD-voltage Symbol Limit Values min. max. 14 V V V V V V V V V V V V V V V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA kV HBM (R = 1.5 k, C = 100 pF) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2 Unit Remarks
V21 V1 V2 V3 V5 V7 V8 V9 V10 V11 V12 V15 V16 V17 V18 V19 V20 V24 V25 V28 V29 V33 V34 V36 V38 I6 I13 I14 I21 I22 I26 I27 I30 I31 I35 I39 VESD
V32 V32 V32 V32 V32 V32 V32 V32 V32 V32 V32 V32 V32 V32 V32 V32 V32 V32 V32 V32 V32 V32 V32 V32
2 2 2 2 2 2 2 2 2 2 2 2
Semiconductor Group
123
TDA 6812-5
Absolute Maximum Ratings (cont'd) TA = 0 to 70 oC; all voltages relatives to VSS Parameter ESD-voltage Junction temperature Storage temperature Thermal resistance system ambient Operating Range Supply voltage Ambient temperature Input frequency range Symbol Limit Values min. max. 6 150 - 40 125 38 kV
o o
Unit
Remarks HBM (R = 1.5 k, C = 100 pF)
VESD7-14 - 6 Tj Tstg R th SA
C C
K/W
V32 TA fI
10 0 0.01
13.2 70 20
V
oC
kHz
Semiconductor Group
124
TDA 6812-5
Characterstics
VS = 12 V; TA = 25 oC; AF-reference level 0 dB = 250 mVrms unless otherwise defined; in
accordance with test circuit 1. I2C Bus preset: Start - 84 - 01,3F - 02,3F - 00,00-03,1F - 04,88 - 05,10 - 06,12-07,12-08,12-09,00-Stop Chip address - Vol LSl 63 - Vol LSr 63 - Vol Pre 0 - Vol HP 31 - Tone lin - Gain 0 dB - Switch byte I, II, II, IV The basic setting for each item in the specifications is always preset; the test conditions only state settings that differ. Details in italics are for explanation of the hex codes, for switching bits only set bits or functions are given.5
Parameter
Symbol
Limit Values min. typ. 58 max. 85
Unit mA
Test Condition
Current consumption I32 Signal Section Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Gain Gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Gain Gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain
V22-1 V21-3 V27-1 V26-3 V31-1 V30-3 V13-1 V14-3 V22-3 V21-3 V27-3 V26-3 V31-3 V30-3 V22-1 V27-1 V31-1 V13-3 V13-1 V22-1 V21-3 V27-1 V26-3 V31-1 V30-3
-2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 -2 4 4 4 -2 4 4 4 4 4 4 4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 6 6 0 6 6 6 6 6 6 6
2 2 2 2 2 2 2 2 2 2 2 2 2 2 8 8 8 2 8 8 8 8 8 8 8
dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 08,32; Stereo; V1 = 0 08,32; Stereo; V1 = 0 08,32; Stereo; V1 = 0 08,32; Stereo; V1 = 0 07,32; Stereo; V1 = 0 07,32; Stereo; V1 = 0 08,32; Stereo; V3 = 0 08,32; Stereo; V3 = 0 07,32; Stereo; V3 = 0 06,32; Stereo; V1 = 0 06,32; Stereo; V3 = 0 09,01; 6 dB 09,01; 6 dB 09,01; 6 dB 09,01; 6 dB 09,01; 6 dB 09,01; 6 dB
Semiconductor Group
125
TDA 6812-5
Characteristics (cont'd) Parameter Gain Gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Gain Gain Max. gain Max. gain Max. gain Max. gain Max. gain Max. gain Gain Gain Min. gain main control Min. gain main control Min. gain precontrol Min. gain precontrol Symbol Limit Values min. typ. 6 6 6 6 6 6 6 6 12 12 12 6 12 0 0 0 0 0 0 0 0 - 70 - 70 - 17 - 17 - 15 - 15 max. 8 8 8 8 8 8 8 8 14 14 14 8 14 2 2 2 2 2 2 2 2 - 65 - 65 - 13 - 13 dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB 09,01; 6 dB 09,01; 6 dB 08,32-09,01; V1 = 0 Stereo; 6 dB 08,32-09,01; V1 = 0 Stereo; 6 dB 08,32-09,01; V1 = 0 Stereo; 6 dB 08,32-09,01; V1 = 0 Stereo; 6 dB 07,32-09,01; V1 = 0 Stereo; 6 dB 07,32-09,01; V1 = 0 Stereo; 6 dB 08,32-09,01; V3 = 0 Stereo; 6 dB 08,32-09,01; V3 = 0 Stereo; 6 dB 07,32-09,01; V3 = 0 Stereo; 6 dB 06,32-09,01; V1 = 0 Stereo; 6 dB 06,32-09,01; V3 = 0 Stereo; 6 dB 08,45; SCART 08,45; SCART 08,45; SCART 08,45; SCART 07,45; SCART 07,45; SCART 06,45; SCART 06,45; SCART 01,08-02,08 Vol LSl 8-Vol LSr 8 01,08-02,08 Vol LSl 8-Vol LSr 8 01,08-02,08 Vol Pre 24 01,08-02,08 Vol Pre 24 4 4 4 4 4 4 4 4 10 10 10 4 10 -2 -2 -2 -2 -2 -2 -2 -2 Unit Test Condition
V13-3 V14-3 V22-3 V21-3 V27-3 V26-3 V31-3 V30-3 V22-1 V27-1 V31-1 V13-3 V13-1 V22-7 V21-8 V27-7 V26-8 V31-7 V30-8 V13-7 V14-8 V22-1 V21-3 V22-1 V21-3
Same values apply for pins 9 thru 12
Semiconductor Group
126
TDA 6812-5
Characteristics (cont'd) Parameter Symbol Limit Values min. Same values apply for pins 7 thru 12 Min. gain Min. gain Flutter and wow typ. - 62 - 62 max. - 57 - 57 2 2 0 0 0 0 0 0 2.5 2.5 2.5 - 3.5 - 3.5 - 3.5 0.1 0.1 0.1 1.25 1.25 1.25 1.25 2 2 3 3 3 -3 -3 -3 0.2 0.2 0.2 2.5 2.5 2.5 2.5 4 4 3.5 3.5 3.5 - 2.5 - 2.5 - 2.5 0.3 0.3 0.3 dB dB dB 03,01; Vol HP 1 03,01; Vol HP 1 01,3F-01,24 02,3F-02,24 Vol LSl 63-36-Vol LSr 63-36 03,1F-03,13 Vol HP 31-19 01,X-01, (X 1) Vol LSl X-Vol LSl (X 1) 01,X-01, (X 1) Vol LSr X-VolLSr (X 1) 01,X-01, (X 1) VolPre X-Vol Pre (X 1) 01,X-01, (X 1) Vol Pre X-Vol Pre (X 1) 01,X-01, (X 1) Vol HP X-Vol HP (X 1) 03,X-03, (X 1) Vol HP X-Vol HP (X 1) 05,1F; Gain max 05,1F; Gain max 05,1F; Gain max 05,01; Gain max 05,01; Gain max 05,01; Gain max 05,X-05, (X 1) Gain X-Gain (X 1) 05,X-05, (X 1) Gain X-Gain (X 1) 05,X-05, (X 1) Gain X-Gain (X 1) Unit Test Condition
V31-1 V30-3
V21-22 V30-31 V22 V21 V22 V21 V30 V31
Same values apply for pins 7 thru 12
Flutter and wow Increment Vol 22 Increment Vol 21 Increment Vol 22 Increment Vol 21 Increment Vol 30 Increment Vol 31 Matrix adjustment Matrix adjustment Matrix adjustment Matrix adjustment Matrix adjustment Matrix adjustment Adj. increment Adj. increment Adj. increment
dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
V22-1 V31-1 V13-1 V22-1 V31-1 V13-1
V22 V31 V13
Semiconductor Group
127
TDA 6812-5
Characteristics (cont'd) Parameter Bass boost Bass boost Bass cutoff Bass cutoff Increment bass Increment bass Treble boost Treble boost Treble cut-off Treble cut-off Increment treble Increment treble Sound linearity Symbol Limit Values min. typ. 15 15 - 12 - 12 1 1 10 10 3 3 12 12 - 12 - 12 1 1 3 3 5 5 2 2 5 5 max. dB dB dB dB dB dB dB dB dB dB dB dB dB 04,8F; f I = 40 Hz Bass max, Treble lin 04,8F; f I = 40 Hz Bass max, Treble lin 04,80; f I = 40 Hz Bass max, Treble lin 04,80; f I = 40 Hz Bass max, Treble lin 04,8X-04.8 (X 1) Bass X-Bass (X 1) 04,8X-04.8 (X 1) Bass X-Bass (X 1) 04,8F; f I = 15 kHz Treble max, Bass lin 04,8F; f I = 15 kHz Treble max, Bass lin 04,8F; f I = 15 kHz Treble max, Bass lin 04,8F; f I = 15 kHz Treble max, Bass lin 04,8X-04, (X 1) 8 Treble X-Treble (X 1) 04,8X-04, (X 1) 8 Treble X-Treble (X 1) 04,88; f I = 40 Hz - 15 kHz Treble, Bass lin 04,88; f I = 40 Hz - 15 kHz Treble, Bass lin 04,8F; fI = 40 Hz Treble lin, Bass max 01,2F-02,2F Vol LSl 47-Vol LSr 47 13 13 Unit Test Condition
V31-1 V21-3 V31-1 V21-3
V21 V22
V22-1 V21-3 V22-1 V21-3
V21 V22 V21 V22
Sound linearity
dB
Response threshold of clipping detector
V1
580
mVrms
Same values apply for pins 3 and 7 thru 12 Channel separation Channel separation Channel separation V21-22 V30-31 V13-14 50 50 50 dB dB dB
V3 or V1 = 600 mVrms V3 or V1 = 600 mVrms V3 or V1 = 600 mVrms
Semiconductor Group
128
TDA 6812-5
Characteristics (cont'd) Parameter Symbol 60 Limit Values min. Crosstalk attenuation IN/OW typ. max. dB Unit Test Condition
VIW = 0; VIN1,3 = 600 mVrms; VIN7-12 = 2 Vrms
08,0X; V1 = 600 mVrms MUTE L 08,0X; V3 = 600 mVrms MUTE R 08,0X; V1 = 600 mVrms MUTE L 08,0X; V3 = 600 mVrms MUTE R 07,0X; V1 = 600 mVrms MUTE L 07,0X; V3 = 600 mVrms MUTE R 06,0X; V3 = 600 mVrms MUTE R 06,0X; V1 = 600 mVrms MUTE L
Muting Muting Muting Muting Muting Muting Muting Muting
1-22 3-21 1-27 3-26 1-31 3-30 3-14 1-13
80 80 80 80 80 80 80 80
dB dB dB dB dB dB dB dB
Same values apply for pins 7 thru 12; V7-12 = 2 Vrms Max. input voltage Max. input voltage Max. input voltage Max. input voltage Max. input voltage Max. input voltage Max. input voltage Max. input voltage Max. input voltage Max. input voltage
V3* V1 V1 V3* V1 V1 V24 V25 V7* V8*
600 600 300 300 300 150 3.4 3.4 2 2
mVrms mVrms mVrms mVrms mVrms mVrms Vrms Vrms Vrms Vrms
V21 1 % V22 1 % V22 1 %; stereo V21 1 %; 09,01; 6 dB V22 1 %; 09,01; 6 dB V22 1 %; 09,01; 6 dB; stereo V21 1 % V22 1 % V22 3 % V21 3 %
* VIN in mono mode without SC2 V3 = 2 Vrms and 1 Vrms
* Full tone control possible when 00,18; Vol Pre 24 Same values apply for pins 9 thru 12 Distortion factor Distortion factor Distortion factor Distortion factor
THD30 THD31 THD30 THD31
0.01 0.01 0.01 0.01
0.1 0.1 0.1 0.1
% % % %
V3 = 250 mVrms V1 = 250 mVrms V3 = 250 mVrms; 03,15
Vol HP 21 V3 = 250 mVrms Vol HP 21
Same values apply for pins 7 thru 12; V7-12 = 600 mVrms Semiconductor Group 129
TDA 6812-5
Characteristics (cont'd) Parameter Distortion factor Distortion factor Distortion factor Symbol Limit Values min. typ. 0.01 0.01 0.01 max. 0.1 0.1 0.2 % % % Unit Test Condition
THD22 THD21 THD22 THD21 THD22 THD21
V1 = 250 mVrms V3 = 250 mVrms V1 = 0.25 Vrms
01,2F-02,2F Vol LSl 47-Vol LSr 47 V3 = 0.25 Vrms 01,2F-02,2F Vol LSl 47-Vol LSr 47 V1 = 250 mVrms; 04.XX Tone random V3 = 250 mVrms; 04.XX Tone random
Distortion factor
0.01
0.2
%
Distortion factor Distortion factor
0.01 0.01
0.4 0.4
% %
Same values apply for pins 7 thru 12; V7-12 = 600 mVrms Distortion factor Distortion factor Antiphase crosstalk sound base Antiphase crosstalk sound base Sound base phase Sound base phase Phase rotation quasi stereo
THD14 THD13
V22-21 V21-22 0.5
0.01 0.01 0.55
0.1 0.1
% %
V3 = 250 mVrms V1 = 250 mVrms V3 = 600 mVrms; fI = 2 kHz; 09,10
Base V3 = 600 mVrms; fI = 2 kHz; 09,10 Base
Same values apply for pins 7 thru 12; V7-12 = 600 mVrms
0.5
0.55
21-22 22-21
150 150
180 180
210 210
deg deg
V1 = 600 mVrms; 09,10
Base; f = 2 kHz V3 = 600 mVrms; 09,10 Base; f = 2 kHz
22-21 22-21 22-21
0 130 - 30
10 180 10
40 230 0
deg deg deg
V3,1 = 600 mVrms;
09,20; QSt; f = 40 Hz
V3,1 = 600 mVrms;
09,20; QSt; f = 700 Hz
V3,1 = 600 mVrms;
09,20; QSt; f = 15 kHz
Semiconductor Group
130
TDA 6812-5
Characteristics (cont'd) Parameter Unweighted SNR Unweighted SNR Unweighted SNR Symbol S/N22 S/N21 S/N22 90 90 70 Limit Values min. typ. 97 97 80 max. dB dB dB Unit Test Condition
VNrms 20 Hz-20 kHz ; V1 = 0.6 Vrms VNrms 20 Hz-20 kHz ; V1 = 0.6 Vrms VNrms 20 Hz-20 kHz ; V1 = 0.6 Vrms
01,27-02,27 Vol LSl 39-Vol LSr 39 VNrms 20 Hz-20 kHz ; V1 = 0.6 Vrms 01,27-02,27 Vol LSl 39-Vol LSr 39
Unweighted SNR
S/N21
70
80
dB
Noise voltage
VN22 VN21
2
10
Vrms Vrms
VNrms 20 Hz-20 kHz ;
01,00-02,00 Vol LSl 0-Vol LSr 0
Noise voltage
2
10
VNrms 20 Hz-20 kHz ;
01,00-02,00 Vol LSl 0-Vol LSr 0
Unweighted SNR Unweighted SNR Unweighted SNR
S/N31 S/N30 S/N31 S/N30
90 90 70
97 97 80
dB dB dB
VNrms 20 Hz-20 kHz ; V1 = 0.6 Vrms VNrms 20 Hz-20 kHz ; V3 = 0.6 Vrms VNrms 20 Hz-20 kHz ; V1 = 0.6 Vrms
03,10; Vol HP 16
Unweighted SNR
70
80
dB
VNrms 20 Hz-20 kHz ; V3 = 0.6 Vrms
03,10; Vol HP 16
Noise voltage Noise voltage Unweighted SNR Unweighted SNR
VN31 VN30
S/N13 S/N14 90 90
2 2 97 97
10 10
Vrms Vrms dB dB
VNrms 20 Hz-20 kHz ;
03,00; Vol HP 0
VNrms 20 Hz-20 kHz ;
03,00; Vol HP 0
VNrms 20 Hz-20 kHz ; V1 = 0.6 Vrms VNrms 20 Hz-20 kHz ; V3 = 0.6 Vrms
Semiconductor Group
131
TDA 6812-5
Characteristics (cont'd) Parameter DC transition 1 bit DC transition 1 bit DC transition 1 bit DC transition 1 bit DC transition 1 bit DC transition 1 bit DC transition 1 bit DC transition 1 bit Design-Related Data Input resistance Input resistance Input resistance Input resistance Input resistance Input resistance Input resistance Input resistance Output resistance Output resistance Output resistance Output resistance Output resistance Output resistance Output resistance Output resistance Symbol V22 V21 V22 V21 V22 V21 V30 V31 Limit Values min. typ. max. 10 10 10 10 10 10 10 10 mV mV mV mV mV mV mV mV 01,X-01,X 1 Vol LSl X-Vol LSl (X 1) 02,X-02, X 1 Vol LSr X-Vol LSr (X 1) 00,X-04, X 1 Vol Pre X-Vol Pre (X 1) 00,X-04, X 1 Vol Pre X-Vol Pre (X 1) 04,X-05, X 1 Tone X-Tone (X 1) 04,X-05, X 1 Tone X-Tone (X 1) 03,X-03, X 1 Vol HP X-Vol HP (X 1) 03,X-03, X 1 Vol HP X-Vol HP (X 1) Unit Test Condition
R1 R3 R7 R8 R9 R 10 R 11 R 12 R 13 R 14 R 21 R 22 R 26 R 27 R 30 R 31
22 22 25 25 25 25 25 25 60 60 60 60 200 200 200 200
k k k k k k k k
Semiconductor Group
132
TDA 6812-5
Characteristics (cont'd) Parameter Symbol min. Identification-Signal Decoder Gain filter op-amp Max. input voltage VCO voltage PLL VCO voltage PLL VCO voltage PLL VCO voltage PLL Limit Values typ. max. Unit Test Condition Test Circuit
V6 V6 V39 V39 V39 V39 V39 V39
2
13 600 1.3 2
14
15
dB V
VIF = 80 mVpp f 35 = 14.6 kHz; V35 = 2.5 V f 35 = 15.625 kHz; V35 = 2.5 V f 35 = 16.6 kHz; V35 = 2.5 V f 35 = 58.4 kHz; V35 = 2.5 V
00,40, Line sync
1 2 2 2 2 2 2
mVpp Function
3
4 4.7
V V V
1.3
VCO voltage PLL
4.7
V
f 35 = 66.4 kHz; V35 = 2.5 V
00,40, Line sync 00,40, Line sync; Xtal 4
VCO voltage PLL
2
3
2
4
V
V ID filter
V36 or V38 when V6 = 0 V 36 - V 36 + V 38 - V 38 = --------------------------------------------------------------------------------- V36* or V38* when V6 = 100 mVpp; m = 50 % V6 VISF VISF
3.4 6.8 dB
f 6 = pilot signal: dual
Gain identificationsignal filter Gain identificationsignal filter
I2C-talk: dual 3.4 6.8 dB
f 6 = pilot signal: stereo; I2C-talk: stereo
V36 test = V36 (V5 = 0) V36 ; V38 test = V38 (V6 = 0) V38
Detection threshold Detection threshold Detection threshold Detection threshold V36 - V36 V38 - V38 900 900 900 900 mV mV mV mV I2C-talk: stereo or dual I2C-talk: stereo or dual I2C-talk: stereo or dual I2C-talk: stereo or dual 3 3 3 3
Semiconductor Group
133
TDA 6812-5
Characteristics (cont'd) Parameter Mono threshold Mono threshold Mono threshold Mono threshold Detection response Detection response Switching threshold f REF-input Switching threshold f REF-input Amplitude crystal oscillator Symbol min. V36 - V36 V38 - V38 0 0 0 0 0.25 0.25 0 3.5 2 0.3 1.08 2.17 4.34 8.68 Limit Values typ. max. 100 100 100 100 0.5 0.5 1.5 mV mV mV mV I2C-talk: mono I2C-talk: mono I2C-talk: mono I2C-talk: mono I2C-talk: stereo or dual; V36 = 1 V I2C-talk: stereo or dual; V38 = 1 V Unit Test Condition Test Circuit 3 3 3 3 3 3 2 2 to = 4.00000 MHz Series rsonance 4 3 09,C8, MPX = 1 s 09,08, MPX = 2 s 09,48, MPX = 4 s 09,88, MPX = 8 s
tdet tdet VH-IL VH-IH V35*
tMPX tMPX
V V Vpp Vpp s s s s
V21
External 1-MHz or 4- V35 MHz clock Multiplexer clock Multiplexer clock Multiplexer clock Multiplexer clock Design-Related Data Filter output resistance Input impedance crystal oscillator Crystal oscillator series resistance Crystal oscillator series resistance
tMPX tMPX tMPX tMPX
R 36,38
110 800 - 600 - 500 - 400 100 300 20
k dB Ptot QU = 1W; 4 MHz Ptot QU = 1W; 12 MHz Ptot QU = 1W; f <15 MHz
f REF input resistance R 35 Z 35
R Q1 R Q3
I2C Bus (SCL, SDA) Edges SCL, SDA Rise time Fall time
tR tF
1 300
s ns
Semiconductor Group
134
TDA 6812-5
Characteristics (cont'd) Parameter Shift register clock SCL Frequency H-pulse width L-pulse width Start Setup time Hold time Stop Setup time Bus free Data change Setup time Hold time Input SCL, SDA Input voltage Input current Output SDA (open collector) Output voltage Output voltage port 1 Output voltage port 1 Symbol min. Limit Values typ. max. kHz s s Unit Test Condition Test Circuit
f SCL tH tL tSUSTA tHDSTA tSUSTO tBUF tSUDAT tHDDAT VIH VIL IIH IIL VQH VQL V15H V15L V15H V15L
0 4 4 4 4 4 4 1 600 2.4
100
s s s s s ns 5.5 1 50 100 V V A A V V V V V V
5.4 0.4
R L = 2.5 k IQL = 3 mA R L = 2.5 k; 09,04 IQL = 3 mA; 09,00 R L = 2.5 k; 02,02 IQL = 3 mA; 09,00
2 2 2 2
VS
0.4
VS
0.4
Semiconductor Group
135
TDA 6812-5
Test Circuit 1 Semiconductor Group 136
TDA 6812-5
Test Circuit 2 Semiconductor Group 137
TDA 6812-5
Test Circuit 3 Semiconductor Group 138
TDA 6812-5
Test Circuit 4 Semiconductor Group 139
TDA 6812-5
Application Circuit 1 Semiconductor Group 140
TDA 6812-5
Application Circuit 2 Semiconductor Group 141
TDA 6812-5
TV-Soundconcept with Dolby-Surround-Option
Semiconductor Group
142
TDA 6812-5
Semiconductor Group
143
TDA 6812-5
I2C Bus Timing Diagram
tSUSTA tHDSTA tH tL tSUDAT tHDDAT tSUSTO tBUF tF tR
Setup time (start) Hold time (start) H-pulse width (clock) L-pulse width (clock) Setup time (data change) Hold time (data change) Setup time (stop) Bus free time Fall time Rise time
All times referred to VIH and VIL values.
Semiconductor Group
144

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